1. Field of the Invention
This invention relates to a planarization process for semiconductor integrated circuit structures. More particularly, this invention relates to an inter-metal-dielectric planarization process that utilizes a sacrificial dielectric layer and an etch back chemistry of SF.sub.6 and Cl.sub.2.
2. Description of the Prior Art
In the formation of integrated circuit structures, layers are patterned to form active devices, such as transistors, passive devices, such as resistors, and metal lines. This patterning of layers often creates uneven surfaces which can cause problems to subsequent overlying layers and devices.
Conventionally, a layer of insulating material, such as silicon oxide, is applied over such uneven surfaces to permit the formation of overlying patterned layers. However, the insulating layer (e.g., silicon oxide) tends to conform to the underlying topography resulting in the creation of a non-planar or stepped surface. It is very difficult to pattern further layers over such an uneven surface using standard lithography techniques.
It has become the customary practice to apply planarizing layers of doped oxides, photoresist and organic-based glass materials, such as "SOG" (Spin On Glass). The insulating layer and the planarization layer are then anisotropically etched to remove the planarizing layer and raised sections of the underlying insulating layer.
However, the layers are not etched evenly because of a "loading effect" which results in a rough surface. The loading effect exists if the etch rate of a layer increases as the etching surface area decreases. Also the difference between the etch rates of the insulating layer and the planarization layer cause an even more uneven surface. Thus, achieving an equal etch rate of both the insulating layer (silicon oxide) and the planarizing layer is very difficult and the etch rate is dependent upon the geometry of the underlying structure.
FIG. 1 shows a process for planarization according to the prior art process. Raised portions 14, e.g., metal lines, are formed on an integrated circuit structure 10. Integrated circuit structure 10 can be a semiconductor wafer, including layers formed in and on the wafer. A conformal insulating layer 20, which may be formed of silicon oxide, is formed over the raised portions 14 and the integrate circuit structure 10. Conformal insulating layers composed of silicon oxide may be formed by O.sub.3 TEOS processes or by electron cyclotron resonance (ECR) oxide plasma deposition as describe in U.S. Pat. No. 4,962,063, Mayden et al. since these oxides can fill-in small geometry volumes better than conventional oxides.
Next, a planarizating layer 30, which may be a doped oxide or spin on glass (SOG), is applied over conformal insulating layer 20 and then the coated structure is subjected to a planarizing etch step (e.g., an anisotropic dry etch) to remove some or all of the planarizing layer 30 and the high regions of the underlying insulating layer 20 as shown in FIG. 3.
However, this process provides a less than optimal planar insulating layer 20 surface as show in FIG. 3. The surface of the planarization layer 20 is not completely planar because of several problems inherent in the prior art process. One problem with the conventional process is that the planarization layer etch rate increases with an increase in the area of exposed silicon dioxide adjacent to the etch site. Therefore, the planarization layer etch rate and the selectivity (S) for any localized region on a wafer may not be constant throughout an etch process. This phenomenon is often referred to as "micro-loading". Moreover, the almost uncontrollable selectivity of planarization layer to insulating layer (oxide) causes uniformity problems, especially when using a CHF.sub.3 and CF.sub.4 etch. Moreover, because of the micro loading effect, the etch back rate of the planarization layer and the insulating layer must be carefully controlled to leave the proper amount of insulating layer over the raised portions.
These problems have prevented achievement of acceptable planarization for a patterned semiconductor structure. What is needed is an approach to planarization of topographies encountered in semiconductor processing that: provides relative insensitivity of planarization layer etch rates to changes in the amount of exposed insulating layer (oxide) area, provides more planar surfaces, and improves the controllability of the planarization process.